1. Field of the Invention
This invention relates generally to solid-state nonvolatile memories, and more particularly to providing a method for increasing effective transistor width in memory arrays with dual bitlines.
2. Description of the Background
Solid-state nonvolatile memories can be formed based on sensing resistance states. One such example is a phase change memory device that utilizes phase change materials to form individual memory cells/elements. Phase change materials can be electrically switched between a generally amorphous, high resistance state and a generally crystalline, low resistance state. The memory elements, depending on the application, can be electrically switched between generally amorphous and generally crystalline local orders or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. Other resistive memory candidates, such as ferroelectric, perovskite, solid electrolytes, or molecular switches, operate in a similar manner, switching between two distinct resistance states upon application of a significant current and/or voltage.
One of the limiting factors in the density with which a non-volatile memory can be fabricated is not the size of the programmable memory element, but the size of the access transistor or other access device co-located with each memory element. The limitation of the access device stems from the scaling of the maximum current supplied by the access device with its size, and thus memory element configurations that can reduce the amount of current required (total power required) in order to switch the memory element are key design considerations. Thus there is a need in the art of memory design for access schemes that maximize current supplied to a memory element, while maintaining unique programming and read access to individual memory elements.